Improving hardware performance of post-quantum cryptography algorithms

نوع: Type: thesis

مقطع: Segment: masters

عنوان: Title: Improving hardware performance of post-quantum cryptography algorithms

ارائه دهنده: Provider: Mohammad Ghafari-Hezaveh

اساتید راهنما: Supervisors: Dr. Hatam Abdoli

اساتید مشاور: Advisory Professors:

اساتید ممتحن یا داور: Examining professors or referees: Dr. Mahdi Abbasi & Dr. Abbas Ramezani

زمان و تاریخ ارائه: Time and date of presentation: 28/06/2022 10:00 AM

مکان ارائه: Place of presentation: Amphitheater

چکیده: Abstract: Quantum computers have much more computing power than classical computers due to their quantum physics properties, and this has created a challenge in the field of public-key cryptography algorithms, which is predicted quantum computers will reach the computational power to break existing public-key cryptography algorithms by 2030. To solve this problem, NIST published a call for post-quantum cryptography algorithms, and some of these algorithms qualified for the third round of the competition. Implementing these algorithms faces challenges such as execution time and resources, and to improve their implementation through various methods such as changes in the computational part or techniques at the level of computer architecture have been used. One of the algorithms that made it to the third round is the CRYSTALS-KYBER algorithm. In this algorithm, by optimizing the NTT module, the execution time is reduced. Usually the implementation of NTT is created with radix-2, but in the proposed method, radix-4 is used, and this reduces the execution time. Changes to NTT are required to implement radix-4 NTT. DIT is used to implement NTT and DIF is used to implement INTT. In NTT and INTT formulas changes are made to the twiddle factors and the values of the twiddle factors stored to the ROM. In the following, we compared radix-4 butterfly unit with radix-2 butterfly unit. By reusing results in CT and GS butterfly units, we need four multiplications, additions, and subtractions, and the structure of radix-4 butterfly unit is mentioned. The memory unit uses eight RAMs to increase read and write speeds, four of which are for writing and the remaining four are for reading. It is also necessary to make corrections to the NTT parameters which are suitable for implementation on Kyber. Next, we implemented the proposed method on two FPGA Artix-7 and Virtex-7 using Vivado software. In the implementation on Artix-7 and Virtex-7 in exchange for a slight increase in the resources, the execution time is reduced

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