Improving hardware performance of post-quantum cryptography algorithms

نوع: Type: پایان نامه

مقطع: Segment: کارشناسی ارشد

عنوان: Title: Improving hardware performance of post-quantum cryptography algorithms

ارائه دهنده: Provider: نادر شیری - رشته کامپیوتر

اساتید راهنما: Supervisors: دکتر حاتم عبدلی

اساتید مشاور: Advisory Professors:

اساتید ممتحن یا داور: Examining professors or referees: آقایان دکتر مهدی عباسی و دکتر رضا محمدی

زمان و تاریخ ارائه: Time and date of presentation: 9 صبح 15 مهر 1402

مکان ارائه: Place of presentation: آمفی تئاتر مهندسی

چکیده: Abstract: While the Internet of Things connects a large number of heterogeneous small devices in a large network and includes many different applications and environments, providing securing the nodes in IoT has become an important issue. This challenge is more difficult for embedded IoT devices Because of their pervasiveness in today's world as well as their limited resources (hardware and energy). Most current public key Cryptography systems, such as RSA and ECC, are insecure against attacks by fast quantum computers. With the view that large-scale quantum computers will be available in the next 10-15 years, NIST begin the process of standardizing post-quantum cryptography To neutralize quantum attacks. Among the various types of quantum-resistant cryptography schemes, Lattice-based cryptography is expanding as a cost-effective and efficient scheme. The proposed schemes Lattice-based PQC, based on the LWE problem and the BR-LWE type, To target resource constrained applications, used binary errors for reduce the key size and achieve a smaller area while maintaining security for light-weight applications, where the implementation of this algorithm faces challenges such as runtime and resource requirements. However, existing works have not well covered the various aspects of the BR-LWE cryptographic scheme, especially in low-complexity hardware implementations. This paper focuses on the development of an efficient hardware implementation of PQC, specifically, the implementation of the BR-LWE based encryption scheme. In this article, an efficient architecture based on LFSR for parallel and effective implementation of polynomial multiplication and its application in the encryption scheme based on INVBR-LWE is presented. By decomposing the polynomial coefficients A and B into multiple groups and executing them simultaneously in two parallel circuits, we have made it possible to reduce the execution time of the entire algorithm. The results of the synthesis on the FPGA chip show that the proposed design has a lower total delay compared to similar works due to the reduction of the execution cycle, and the ADP criterion of the proposed method has been reduced by 35%. According to the obtained results, the proposed design can be extended for use in light-weight applications