Improving performance of PQC algorithms by optimizing arithmetic operations

نوع: Type: thesis

مقطع: Segment: masters

عنوان: Title: Improving performance of PQC algorithms by optimizing arithmetic operations

ارائه دهنده: Provider: Masoomeh Mahmoudi

اساتید راهنما: Supervisors: Dr.Abdoli

اساتید مشاور: Advisory Professors:

اساتید ممتحن یا داور: Examining professors or referees: Dr.Ramezani, Dr.Khotanlou

زمان و تاریخ ارائه: Time and date of presentation: 2024

مکان ارائه: Place of presentation: Faculty of Engineering

چکیده: Abstract: Due to the development of scalable and fault-tolerant quantum computers, it is anticipated that the security of common public key cryptographic algorithms such as RSA will be vulnerable. The National Institute of Standards and Technology (NIST) is in the process of standardizing post-quantum cryptography (PQC), which is designed to withstand attacks by quantum computers. This thesis aims to optimize the hardware implementation of one of the Lattice-based algorithms with the "Saber" public key encapsulation mechanism (one of the final candidates), whose security is based on Mod-LWR, which consists of power 2 modules to achieve flexibility and high security and efficiency. Uses. The goal in this lightweight implementation is to use minimal resources with minimal execution time. This research focuses on exploiting efficient hardware architectures to achieve higher performance, while maintaining security against quantum attacks. In this research, a method to improve the efficiency of the addition operation in the SABER algorithm is presented. Considering that polynomial multiplication plays an essential role in the performance of the module and public key cryptography, a parallel polynomial multiplier architecture is proposed that solves the memory access limitation problems. In the proposed method, instead of using 256 MAC units with 13 entries bit, using a MAC unit and using CSA instead of RCA. These changes make the addition operation to be performed with less delay. In other words, the transmission of the numerical digit is removed every time the addition operation is performed and will be done only at the last stage, and as a result, the delay time of the publication and the total time of the addition operation will be significantly reduced. The synthesis results show that this method provides a significant improvement in the efficiency of the SABER algorithm while the memory access limitations are also considered. The synthesis results show that the proposed scheme significantly improves the execution time cycle by reducing resource consumption. Specifically, the proposed architecture runs at a frequency of 250 MHz and the ATP is improved by 40%. This method paves the way for the development of secure post-quantum cryptographic algorithms in resource-constrained environments